Hi Olell,
Did you confirm if this was the cause of your issue? I have a similar issue on a design, with 1v8 being used as `DDR_VDDQ[1..3]`, and only seeing `RKUART` on the debug port. I am looking at making the change to use 1v35, but obviously it's not trivial to quickly test.

Thanks,
Andre

Has there been a new version of the schematics released? The copy at https://files.luckfox.com/wiki/Luckfox- ... ro_Max.pdf still appears to show the 1v8 rail being used for VCC_DDR/DDR_VDDQ_n.