ESP-hosted

2024-09-30 0:45

Hi,

Since I need a WiFi connection, I've been trying for a week, but without success. I chose ESP-hosted as a WiFi platform because the speed and availability are suitable for me.
I have a problem to set SPI interface in .dts. Namely, I need the SPI to be the master in SPI mode 2 or 3, and to have GPIO on pins 53, 52 and 59. The SPI interface needs normal pins, meaning MISO, MOSI, CLK and CS0.
My question is how do I achieve this in a .dts file?
And one more question: Is SPI sharing possible between two devices with, of course, an additional CS0 pin?

2024-09-30 1:49

Hello, your device configuration requirements are directly added in the corresponding DTS file (sdk/config/dts_config).

Code: Select all

&spi0 {
	status = "okay";
};

In the corresponding rv1103-luckfox-pico-ipc.dtsi, all the relevant pins of the spi have been added to the pinctrl

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	pinctrl-0 = <&spi0m0_clk &spi0m0_miso &spi0m0_mosi &spi0m0_cs0>;

If you need to add a new device to share the SPI, you can use the spi0m0_cs1 and change the PINCTRL-0 to

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	pinctrl-0 = <&spi0m0_clk &spi0m0_miso &spi0m0_mosi &spi0m0_cs0 &spi0m0_cs1>;

The other pins are GPIO functions by default if not set, and do not need to be configured

2024-09-30 11:13

Okay, thanks. I will try that configuration now.

2024-09-30 13:30

I can now confirm that ESP-hosted has been successfully ported to Luckfox-pico. It works very well !

2025-12-22 0:54

freetoair wrote: ↑2024-09-30 13:30 I can now confirm that ESP-hosted has been successfully ported to Luckfox-pico. It works very well !

hey, do you mind to post manual here?

2025-12-22 14:08

Im my case I am using pins 48, 49, 50, 51 for SPI communication, however, getting errors:
[ 81.511209] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[ 81.528056] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[ 81.528328] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
[ 81.528345] cfg80211: failed to load regulatory.db
[ 81.764967] esp32_spi: spi_dev_init: Using SPI MODE 2
[ 81.765066] rockchip-spi ff500000.spi: chipselect 0 already in use
[ 81.765100] esp32_spi: spi_dev_init: Failed to add new SPI device
[ 82.204824] esp32_spi: spi_init: Failed Init SPI device
[ 82.444940] esp32_spi: spi_dev_init: Using SPI MODE 2
[ 82.445041] rockchip-spi ff500000.spi: chipselect 0 already in use
[ 82.445075] esp32_spi: spi_dev_init: Failed to add new SPI device
[ 82.884907] esp32_spi: spi_init: Failed Init SPI device
[ 142.272021] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /spi@ff500000/status
[ 142.272041] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /spi@ff500000/pinctrl-0
[ 142.272054] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /spi@ff500000/spidev@0/status
[ 142.272064] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /spi@ff500000/spidev@0/spi-max-frequency
[ 148.630410] OF: overlay: find target, node: /fragment@1, path '/spi@ff500000/fbtft@0' not found
[ 148.630431] OF: overlay: init_overlay_changeset() failed, ret = -22

My DT records

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&spi0 { 
    status = "okay"; 
    pinctrl-0 = <&spi0m0_clk &spi0m0_miso &spi0m0_mosi &spi0m0_cs0>;
    spidev@0 { 
        compatible = "spidev"; 
        reg = <0>; 
        spi-max-frequency = <50000000>; 
    }; 
    fbtft@0 { 
        status = "disabled"; 
    }; 
};