Luckfox Lyra Ultra W Trying to achieve 50Mhz on SPI0
Posted: 2026-01-21 8:25
Short Problem Description:
I'm experiencing SPI speed limitations on RK3506B. When trying to achieve the documented 50 MHz SPI speed, the actual measured throughput only reaches about 30 Mbps maximum.
What I've tried:
Configured SPI0 in DTS with assigned-clock-rates = <100000000> and spi-max-frequency = <50000000>
Tested using Python scripts that measure buffer transfer times
Real-world measurements show ~30 Mbps maximum, regardless of requested speed settings
Current DTS configuration:
dts
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0m0_pins>;
rockchip,rx-sample-delay-ns = <10>;
rockchip,cs-setup-ns = <10>;
rockchip,cs-hold-ns = <10>;
clock-frequency = <100000000>;
clocks = <&cru CLK_SPI0>;
clock-names = "spiclk";
assigned-clocks = <&cru CLK_SPI0>;
assigned-clock-rates = <100000000>;
spidev@0 {
compatible = "rockchip,spidev";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
The issue:
Despite proper DTS configuration and requesting 50 MHz, the actual SPI clock measured on the CLK pin shows only about 30 MHz maximum. The BAUDR register appears to be stuck at divider 4, giving ~23.44 MHz from the 187.5 MHz parent clock, but real throughput is even lower.
Questions:
Is there a known hardware limitation in RK3506 that prevents reaching 50 MHz SPI?
Are there specific clock configurations or pinctrl settings required for high-speed SPI?
Has anyone successfully achieved 50 MHz SPI on RK3506?
Should I try SPI1 instead of SPI0?
Additional info: Testing was done with Python's spidev interface, measuring actual transfer times of data buffers to calculate real throughput.
I'm experiencing SPI speed limitations on RK3506B. When trying to achieve the documented 50 MHz SPI speed, the actual measured throughput only reaches about 30 Mbps maximum.
What I've tried:
Configured SPI0 in DTS with assigned-clock-rates = <100000000> and spi-max-frequency = <50000000>
Tested using Python scripts that measure buffer transfer times
Real-world measurements show ~30 Mbps maximum, regardless of requested speed settings
Current DTS configuration:
dts
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0m0_pins>;
rockchip,rx-sample-delay-ns = <10>;
rockchip,cs-setup-ns = <10>;
rockchip,cs-hold-ns = <10>;
clock-frequency = <100000000>;
clocks = <&cru CLK_SPI0>;
clock-names = "spiclk";
assigned-clocks = <&cru CLK_SPI0>;
assigned-clock-rates = <100000000>;
spidev@0 {
compatible = "rockchip,spidev";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
The issue:
Despite proper DTS configuration and requesting 50 MHz, the actual SPI clock measured on the CLK pin shows only about 30 MHz maximum. The BAUDR register appears to be stuck at divider 4, giving ~23.44 MHz from the 187.5 MHz parent clock, but real throughput is even lower.
Questions:
Is there a known hardware limitation in RK3506 that prevents reaching 50 MHz SPI?
Are there specific clock configurations or pinctrl settings required for high-speed SPI?
Has anyone successfully achieved 50 MHz SPI on RK3506?
Should I try SPI1 instead of SPI0?
Additional info: Testing was done with Python's spidev interface, measuring actual transfer times of data buffers to calculate real throughput.