Luckfox Forums

We are using a Luckfox Pico Ultra Rev 2.0 (RV1106) in an embedded security product and want to add a TI TPL5010 external watchdog for recovery from a Linux/kernel hang.

Proposed interface:

Pico Ultra remains continuously powered from 5 V.
TPL5010 operates at 3.3 V.
Open-drain RSTn connects to the non-ground pad of Key2 RESET/NPOR.
Reset pulse duration is approximately 320 ms.
GPIO1_B2/GPIO42 is used for DONE.
GPIO1_B3/GPIO43 is used for WAKE.
UART2_M1 will be disabled.

Please confirm:

Is the Key2 non-ground pad suitable for an external open-drain watchdog reset?
Should RSTn connect after R43 at the Key2 pad or directly to NPOR?
What external series-resistor value is recommended? Our attached schematic shows a provisional 680 Ω.
Is a 320 ms LOW reset pulse acceptable?
Are GPIO42 and GPIO43 available as 3.3 V GPIOs when UART2_M1 is disabled?

The proposed circuit schematic is attached. We need confirmation before freezing our production PCB.

Thank you.

First of all, we apologize that we do not provide technical support for hardware design validation, as we have no way to replicate the final results. Additionally, please note that the RV1106 has built-in hardware watchdog, which is capable of handling most scenarios that require a watchdog function.