Hi,
I did a post yesterday but it seems to have vanished...
I have a custom board with the Core1106 equipped with dual OV9732. I have problems getting them to work. The both enter clock HS mode, readback of the camera registers are accurate but no frames are received, no SoF are detected, no errors indicated.
Any help is appreciated.
Thanks,
Jan
This is the relevant DTS for the cameras:
/* I2C3 for Camera 0 (OV9732) */
&i2c3 {
status = "okay";
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3m2_xfer>;
ov9732_0: ov9732@10 {
compatible = "ovti,ov9732";
status = "okay";
reg = <0x10>;
clocks = <&cru MCLK_REF_MIPI0>;
clock-names = "xvclk";
assigned-clocks = <&cru CLK_REF_MIPI0>;
assigned-clock-parents = <&xin24m>;
assigned-clock-rates = <24000000>;
pinctrl-names = "default";
pinctrl-0 = <&mipi_refclk_out0>;
reset-gpios = <&gpio3 RK_PD3 GPIO_ACTIVE_LOW>;
avdd-supply = <&vcc_mipi>;
dovdd-supply = <&vcc_1v8>;
dvdd-supply = <&vcc_1v8>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "OV9732";
rockchip,camera-module-lens-name = "default";
port {
ov9732_0_out: endpoint {
remote-endpoint = <&csi_dphy1_input0>;
data-lanes = <1>;
rockchip,hs-settle-delay-ns = <140>;
link-frequencies = /bits/ 64 <360000000>;
};
};
};
};
/* I2C4 for Camera 1 (OV9732) */
&i2c4 {
status = "okay";
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c4m2_xfer>;
ov9732_1: ov9732@36 {
compatible = "ovti,ov9732";
status = "okay";
reg = <0x36>;
clocks = <&cru MCLK_REF_MIPI1>;
clock-names = "xvclk";
assigned-clocks = <&cru CLK_REF_MIPI1>;
assigned-clock-parents = <&xin24m>;
assigned-clock-rates = <24000000>;
pinctrl-names = "default";
pinctrl-0 = <&mipi_refclk_out1>;
reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
avdd-supply = <&vcc_mipi>;
dovdd-supply = <&vcc_1v8>;
dvdd-supply = <&vcc_1v8>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "OV9732";
rockchip,camera-module-lens-name = "default";
port {
ov9732_1_out: endpoint {
remote-endpoint = <&csi_dphy5_input0>;
data-lanes = <2>;
rockchip,hs-settle-delay-ns = <140>;
link-frequencies = /bits/ 64 <360000000>;
};
};
};
};
&csi2_dphy_hw {
clocks = <&cru PCLK_MIPICSIPHY>,
<&cru MCLK_REF_MIPI0>,
<&cru MCLK_REF_MIPI1>;
clock-names = "pclk", "mclk_ref_mipi0", "mclk_ref_mipi1";
status = "okay";
};
/* MIPI CSI-2 DPHY1 for Camera 0 (CSI0 interface, single lane) */
&csi2_dphy1 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
csi_dphy1_input0: endpoint@1 {
reg = <1>;
remote-endpoint = <&ov9732_0_out>;
data-lanes = <1>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy1_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi0_csi2_input>;
};
};
};
};
/* MIPI CSI-2 DPHY2 for Camera 1 (CSI1 interface, single lane) */
&csi2_dphy2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
csi_dphy5_input0: endpoint@1 {
reg = <1>;
remote-endpoint = <&ov9732_1_out>;
data-lanes = <2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy5_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi3_csi2_input>;
};
};
};
};
/* MIPI CSI2 controller for Camera 0 */
&mipi0_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi0_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy1_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi0_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi0_in>;
};
};
};
};
/* MIPI CSI2 controller for Camera 1 */
&mipi1_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi3_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy5_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi3_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi1_in>;
};
};
};
};
&rkcif {
status = "okay";
/* Remove inherited mipi_pins to avoid pinmux conflicts with camera MCLK outputs */
/delete-property/ pinctrl-names;
/delete-property/ pinctrl-0;
};
&rkcif_mipi_lvds {
status = "okay";
port {
cif_mipi0_in: endpoint {
remote-endpoint = <&mipi0_csi2_output>;
};
};
};
&rkcif_mipi_lvds_sditf {
status = "okay";
port {
mipi_lvds_sditf: endpoint {
remote-endpoint = <&isp_in>;
};
};
};
&rkcif_mipi_lvds1 {
status = "okay";
port {
cif_mipi1_in: endpoint {
remote-endpoint = <&mipi3_csi2_output>;
};
};
};
&rkcif_mipi_lvds1_sditf {
status = "okay";
port {
mipi_lvds1_sditf: endpoint {
remote-endpoint = <&isp_in1>;
};
};
};
&rkisp {
status = "okay";
};
&rkisp_vir0 {
status = "okay";
port@0 {
isp_in: endpoint {
remote-endpoint = <&mipi_lvds_sditf>;
};
};
};
&rkisp_vir1 {
status = "okay";
port@0 {
isp_in1: endpoint {
remote-endpoint = <&mipi_lvds1_sditf>;
};
};
};
/* Pinctrl configuration */
&pinctrl {
/* Camera clock and reset pins for Camera 0 */
camera {
cam_clk0_pins: cam-clk0-pins {
rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
cam_0_reset_gpio: cam-0-reset-gpio {
rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>;
};
/* Camera clock and reset pins for Camera 1 */
cam_clk1_pins: cam-clk1-pins {
rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
cam_1_reset_gpio: cam-1-reset-gpio {
rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
/* I2C3 pins for Camera 0 */
i2c3 {
i2c3m2_xfer: i2c3m2-xfer {
rockchip,pins = <3 RK_PD1 3 &pcfg_pull_none_smt>,
<3 RK_PD2 3 &pcfg_pull_none_smt>;
};
};
/* I2C4 pins for Camera 1 */
i2c4 {
i2c4m2_xfer: i2c4m2-xfer {
rockchip,pins = <3 RK_PC7 3 &pcfg_pull_none_smt>,
<3 RK_PD0 3 &pcfg_pull_none_smt>;
};
};